| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 6946623 | Microelectronics Reliability | 2015 | 5 Pages |
Abstract
A cross-sectional view of the SEB damage showed that melting of the SiC occurred and cracks were formed in the nâ drift region due to the highly localized SEB current. This indicates that the maximum lattice temperature reached the sublimation temperature of SiC. The location of the simulated peak lattice temperature agreed closely with the position of the observed SEB damage. This demonstrated that the main mechanism triggering SEB in SiC power MOSFETs is not parasitic npn-transistor action, but a shift in the peak electric field and the punch-through in the n+ source diffusion region, similar to the case for SiC power diodes.
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Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Tomoyuki Shoji, Shuichi Nishida, Kimimori Hamada, Hiroshi Tadano,