| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 6946671 | Microelectronics Reliability | 2015 | 6 Pages |
Abstract
This paper outlines a proposed technique; perform Platinum (Pt) deposition on the selective area to slow down the side-edging effect. This proposed technique is easy and less skillset dependent to deprocess sample for defect identification analysis.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
H.H. Yap, P.K. Tan, G.R. Low, M.K. Dawood, H. Feng, Y.Z. Zhao, R. He, H. Tan, J. Zhu, B. Liu, Y.M. Huang, D.D. Wang, J. Lam, Z.H. Mai,