| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 6947008 | Microelectronics Reliability | 2012 | 4 Pages |
Abstract
Threshold voltage (VT) and mobility (μ) shifts due to process related variability and Channel-Hot Carrier (CHC) degradation are experimentally characterized in strained and unstrained pMOSFETs. A simulation technique to include the time-dependent variabilities of VT and μ in circuit simulators is presented and used to evaluate their effects on CMOS inverters performance.
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Authors
N. Ayala, J. Martin-Martinez, R. Rodriguez, M.B. Gonzalez, M. Nafria, X. Aymerich, E. Simoen,