BTI reliability of ultra-thin EOT MOSFETs for sub-threshold logic

A first study of the BTI reliability of a 6 Å EOT CMOS process for potential application in sub-threshold logic is presented. Considerable threshold voltage shifts are observed also for sub-threshold operation. The observed shifts convert to a remarkable current reduction due to the exponential dependence of current on Vth in this operating regime. Moreover, the pMOS is observed to degrade significantly more w.r.t. the nMOS device, inducing a detrimental Vth-imbalance. A proper device failure criterion is proposed, based on simulation of the DC robustness of an inverter logic circuit.