| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 6947241 | Microelectronics Reliability | 2011 | 15 Pages |
Abstract
We demonstrate here for the first time that it is possible by a bottom-up approach to build transistor- and gate-level models with enough accuracy to allow direct comparison with experimental degradations at system-level. This work opens new ways to optimize high level digital systems with respect to aging with great accuracy.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
V. Huard, N. Ruiz, F. Cacho, E. Pion,