| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 6947270 | Microelectronics Reliability | 2011 | 4 Pages |
Abstract
⺠PBTI was measured on low EOT triple gated FinFETs with TiN/HfO gate stack to assess their reliability. ⺠TiN gate reduces SiO interlayer and increases PBTI degradation. ⺠Wider devices present a higher degradation which may be caused by a higher density of defects on the top-wall. ⺠PBTI degradation could be a problem for ultra low EOT for both planar and FinFET devices.
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Authors
P.C. Feijoo, M. Cho, M. Togo, E. San Andrés, G. Groeseneken,