Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6947312 | Microelectronics Reliability | 2011 | 4 Pages |
Abstract
The sensitivity of stress-induced-voiding to structural layouts is investigated using Finite Element Modeling and is validated experimentally. A method is proposed to quantify the stress gradient and has been applied to different structural layouts at different temperatures. It is shown that different temperature ranges need to be addressed for stress-induced-voiding storage tests on structures with varying layouts. Experimental results do not show failures at temperatures outside these range which agree well with the modeling results. Also our modeling predicts higher stress gradients for structures with VIA's positioned in the middle of metal planes compared to those with VIA's positioned at the edge of such plane.
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Authors
M. Lofrano, K. Croes, I. De Wolf, C.J. Wilson,