Identifying electrical mechanisms responsible for functional failures during harsh external ESD and EMC aggression

For particular applications, system level stresses such as EMC stress or ESD (IEC61000-4-2) are directly applied to the integrated circuits with no external protections. Consequently, the integrated circuits have to be designed for reliability in order to stay alive but also to guarantee the normal operations during severe electrical aggressions. Unfortunately, the simulation of functional failures during severe ESD or EMC events remains very challenging for analog products due the frequency domain and to the high current injection mechanisms. This paper describes a test method to identify the design functions and the physical mechanisms that lead to functional failures when integrated circuits are submitted to system level stress.