Reliability impact due to high current, lattice and hot carriers temperatures on β(2×2) matrix ESD power devices for advanced CMOS technologies

The main purpose of this paper is to present the behavior of a β(2×2) matrix ESD power device with the effects of high ESD current, lattice and hot carriers temperatures. The beta matrix is a candidate for ESD device network for advanced CMOS technologies. This demonstrator is done in C45 & C32 nm CMOS technologies. The high ESD current, lattice temperature and hot carriers temperature are study thanks to 3D TCAD simulations in ACS stimulus. Thus, it is possible to identify the potential weakness point and optimize the topology of this kind of power device. Moreover, the IV curves are measured in TLP condition to determine the ESD response.