Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
6947381 | Microelectronics Reliability | 2011 | 4 Pages |
Abstract
During the qualification of a new Advanced Bipolar, CMOS, DMOS (A-BCD) technology some typical failure modes were observed in this SOI process. After a short introduction of the technology and its areas of application three different failure modes will be discussed. The failures initiated during HTOL test are localized with standard PEM/OBIRCH analysis techniques. Main focus will be on the physical defects at the origin of the fail and the different techniques to reveal them. The failures are observed within the Shallow Trench Isolation (STI) module of the High Voltage components and along the edge of the Medium Trench Isolation (MTI). The root causes and the possible corrective actions will be discussed when applicable.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
J.G. van Hassel, G.A.D. Bock, G. van den Berg,