Shaping electrical field in heterostructure transistors

The decrease of the electron transit time in FETs is achieved mainly by design of short transistors and minimization of scattering in the intrinsic layer of the HEMT channel. A penalty of this miniaturization trend is the creation of a poorly controlled, extremely high electric field along the channel of a transistor. The non-linear distribution of the electric field along the channel of HEMTs leads to the reduction of mobility by a factor of 5-7, causing sequential worsening of the performance parameters, such as gain (gm) and cut-off frequency (ft). The appearance of hot electrons around the drain is another issue on a long list of problems resulting from extreme field profiles. Fundamental dependence of electron velocity on electrical field strength was the foundation of field tailoring in variety of multi-gate transistors. In recent years, the intensified research was focused on reshaping the field profile by using various topologies of additional electrodes, called Field Plates (FPs), such as Overlapping Gate structures, Detached FP design, Stacked 2- and 3-floor FP systems, and others. The current study presents a review of the advantages and drawbacks of various HEMT designs where additional field plates were used. Although most of the FP topologies were used to increase the breakdown voltage of the new transistors, we offer another application for the field plates. They can be used to improve the average electron velocity. It is also shown that a new pHEMT with quasi-constant gm can be designed using FPs.