Process integration and nanometer-scale electrical characterization of crystalline high-k gate dielectrics

Crystalline praseodymium oxide (Pr2O3) high-k gate dielectric has been successfully integrated into a polysilicon gate CMOS technology. Fully functional MOSFETs with an equivalent oxide thickness (EOT) of 1.8 nm and gate leakages below 10−6 A/cm2 have been fabricated. However, at this early stage of development the transistors show Vt-instabilities and unusual high gate leakage for L > 10 μm. As a first attempt to explain the observed macroscopic device characteristics, topographical and electrical measurements at the nanometer scale have been performed directly on the Pr2O3 surface by Conductive Atomic Force Microscopy (C-AFM). This technique allows to discriminate between structural defect sites and charge trapping centers.