Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
9672276 | Microelectronics Reliability | 2005 | 5 Pages |
Abstract
Effects of constant voltage stress (CVS) on gate stacks consisting of an ALD HfO2 dielectric with various interfacial layers were studied with time dependent sensing measurements: DC I-V, pulse I-V, and charge pumping (CP) at different frequencies. The process of injected electron trapping/de-trapping on pre-existing defects in the bulk of the high-κ film was found to constitute the major contribution to the time dependence of the threshold voltage (Vt) shift during stress. The trap generation observed with the low frequency CP measurements is suggested to occur within the interfacial oxide layer or the interfacial layer/high-κ interface, with only a minor effect on Vt.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Chadwin D. Young, Gennadi Bersuker, Yuegang Zhao, Jeff J. Peterson, Joel Barnett, George A. Brown, Jang H. Sim, Rino Choi, Byoung Hun Lee, Peter Zeitzoff,