| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 9672366 | Microelectronics Reliability | 2005 | 5 Pages |
Abstract
Analytical evaluation of capacitances of interconnections in VLSI circuits is based on empirical equations formulated for basic typical structures combined to model more complex geometric configurations. In this paper this procedure of addition of subregions contribution to the total capacitance is verified for lines crossing in several metallization levels. As a result of simulation experiments simplified but more accurate procedure of evaluation of this capacitance was proposed.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
A. Jarosz, A. Pfitzner,