A low-cost high-speed self-checking carry select adder with multiple-fault detection

Employing cost-efficient, high-speed and fault-tolerant processing units is an essential goal in the design of current processors. In this paper, the carry select adder (CSeA) as one of the fastest adders is augmented respecting multiple-fault detection, delay, power and required area. In this way, based on the concept of a self-checking full adder, an m-bit logic-optimized self-checking single-stage CSeA is designed in which at most m concurrent faults can be detected. Then, based on a delay analysis, a new grouping structure for the self-checking multi-stage CSeA apart from the conventional square-root (SQRT) grouping is proposed to optimize the overall delay for different adder sizes. The proposed grouping structure decreases the power overhead, as well. Experimental results show that as well as an acceptable multiple-fault detection capability, noticeable improvements are achieved in delay and power consumption compared to the previous self-checking CSeA designs. The proposed CSeA reaches in average 20% power reduction and 34% speed improvement in different sizes compared to the best existing design.