Article ID Journal Published Year Pages File Type
10364121 Integration, the VLSI Journal 2005 8 Pages PDF
Abstract
This paper presents ringed bit-parallel systolic multipliers for computing AB+C over a class of finite fields GF(2m), in which all elements are represented using a root of an all-one polynomial or an equally spaced polynomial. Compared to other related multipliers, the proposed multipliers reveal properties of lower hardware complexity, lower latency and free of global connection. Furthermore, we proposed a general rule to plan the multipliers. This rule makes the planning easy.
Related Topics
Physical Sciences and Engineering Computer Science Hardware and Architecture
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