Design and optimization of MOS current mode logic for parameter variations

An automated optimization-based design strategy is proposed for MOS current mode logic (MCML) circuits to overcome the complexities of the design procedure. The proposed design methodology determines the values of the design variables that achieve minimum power dissipation while attaining the required performance. Furthermore, comprehensive analytical formulations of the design parameters associated with MCML circuits are presented to provide guidelines for MCML designers. The proposed design methodology has the advantages of speed, accuracy, and ability to include a large number of parameters in the design problem. Moreover, a formulation for the impact of parameter variations on MCML operation is presented. The proposed strategy is used to design two popular circuits in a 0.18μm CMOS technology, namely; the ring oscillator and clock distribution network drivers with an average error from the required performance within 8%. The dependence of the circuit parameters on parameter variations is used with the design methodology to redesign the same circuits while considering parameter variations. Furthermore, the impact of parameter variations as technology scales down is investigated to highlight the importance of designing for variability in future CMOS technologies.