Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
10364392 | Integration, the VLSI Journal | 2005 | 24 Pages |
Abstract
The paper presents an accurate analysis of the correlation between high-level fault models and the gate-level stuck-at fault model and it proposes a strategy to map high-level faults into logic-level faults. Thus, functional verification, based on a high-level fault model, can be performed by exploiting the capability of state of the art logic-level ATPGs. Experimental results highlight the effectiveness of the methodology.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
F. Fummi, C. Marconcini, G. Pravadelli,