A 1.33 μW 10-bit 200KS/s SAR ADC with a tri-level based capacitor switching procedure

A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) using an energy-efficient tri-level based capacitor switching procedure is presented. The proposed switching procedure achieves 97.66% less switching energy when compared to the conventional method. The number of unit capacitors is reduced by a factor of 4 over that of conventional architecture as well. To make the power consumption of the comparator scale down with respect to the comparison rate, the fully dynamic comparator is used. Moreover, the dynamic logic circuit is implemented to further reduce the power of digital circuits. The ADC is implemented in a 0.18 μm 1P6M CMOS technology. At 1.0-V power supply and 200KS/s, the ADC achieves an SNDR of 60.54 dB and consumes 1.33 μW, resulting in a figure-of-merit (FOM) of 7.7 fJ/conversion-step. The ADC core occupies an active area of only 230×400 µm2.