Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
10364883 | Microelectronics Journal | 2013 | 7 Pages |
Abstract
The traditional current-reused circuit with a wide tuning range of 17.2% is presented in the first chip. It has a phase noise-118Â dBc/Hz at 1Â MHz offset and 5Â mW core power dissipation with a voltage supply under 1.5Â V. The performance of FOM is as high as â191.8Â dBc/Hz. Extra NMOS cross-coupled pairs inside the traditional current-reused circuit in the second chip is proposed to speed up the oscillation and stability. The phase noise is â106.19Â dBc/Hz and the core power dissipation is 3Â mW with a voltage supply under 1.5Â V. For the third chip, two dc level shifters are adopted to improve the symmetry of the output signal and to decrease noise interference. The phase noise and core power are -106.9Â dBc/Hz and 2.88Â mW, respectively. It also has a high performance of FOM with â182.4Â dBc/Hz.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Meng-Ting Hsu, Wei-Jhih Li, Chien-Ta Chiu,