Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
10364886 | Microelectronics Journal | 2013 | 7 Pages |
Abstract
This work presents a full-division-range programmable frequency divider with 50% duty-cycle output. The proposed programmable frequency divider includes a programmable counter (PC) and duty-cycle-improved circuit (DCIC) to achieve full-division-range, low-area, and close-to-50% duty-cycle output from an input clock with an arbitrary duty cycle. A chip was fabricated using 0.18-μm standard CMOS process with a 1.8-V power supply. The experimental results show that the proposed programmable frequency divider can operate correctly when input clock frequency ranges from 1 MHz to 1 GHz and division ratio ranges from 1 to 63. For an input divisor of 20 with input clock frequencies of 700 and 1 MHz and duty cycles of 20% and 99.5%, the output duty cycles were 50.4% and 50%, respectively. The total power consumption of the proposed programmable frequency divider was only 0.62 mW at 700 MHz, and the active die area was only 0.125Ã0.05 mm2.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Yu-Lung Lo, Jhih-Wei Tsai,