A 7b 400 ​MS/s pipelined SAR ADC in 65 ​nm CMOS

This paper presents a 7-bit 400-MS/s pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with high reliability. To meet the high demand for medium resolution and high sampling speed, a modified switching scheme is adopted to resolve charge leakage problem and to improve the reliability of SAR ADC. Compared to the conventional architecture, the modified bootstrapped switch which uses two sampling MOSFETs is employed to increase the uniformity of sampling voltage and save the chip area. In addition, three parallel comparators are controlled by a novel asynchronous clock generator to minimize the latching error. The measurement result shows that the ADC, implemented in the 65-nm CMOS process, achieves the 40.83 dB signal-to-noise and distortion ratio (SNDR) and 64.75 dB spurious-free dynamic ranges (SFDR) at 400-MHz sampling frequency without additional digital calibration.