A 65Â nm CMOS key establishment core based on tree parity machines

A low-area ASIC implementation of a fully-synthesized symmetric key establishment architecture based on tree parity machines (TPMs) in 130 nm and 65 nm standard-cell CMOS technologies is presented. The proposed circuit architecture has a re-keying characteristic enabled by two new circuit implementations. The behavioral simulations shows that synchronization time can be reduced from 1.25 ms to less 0.7 ms with a weight misalignment of 20% in re-keying mode. Relative area and power consumption are studied by comparing synthesized TPMs with an implementation of a CRC16 error detection code used within security applications. Scalability of the architecture is shown by mean of a proposed figure of merit. Further verification is applied for fabrication in 130 nm CMOS technology.