Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
4970656 | Integration, the VLSI Journal | 2017 | 12 Pages |
Abstract
Aiming to tackle the permanent faults on the router components, we propose a high performance, high reliability and low cost router design based on a generic 2-stage router. Five fault tolerant strategies are employed in our reliable router. We exploit an ECC detection and virtual channel closing strategy for input buffer faults, a double routing strategy for the routing computation (RC) faults, a default winner strategy for the virtual allocation (VA) faults, a runtime arbiter selection strategy for the switch allocation (SA) faults and a double bypass bus strategy for the crossbar faults. Different from previous reliable routers, our design leverages the feature of pipeline optimization and routing algorithm to maintain the performance in fault tolerance especially under heavy network loads. Besides, our proposed router provides higher reliability with lower hardware consumption than previous reliable router designs.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Lu Wang, Sheng Ma, Chen Li, Wei Chen, Zhiying Wang,