Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
4970697 | Integration, the VLSI Journal | 2017 | 11 Pages |
Abstract
Both analytic predictions and simulation results for the method proposed here indicate real estate benefits and test time savings in comparison to other reported techniques. The proposed refresh re-use based transparent test technique provides a cost effective solution by providing facility for periodic tests of DRAM without requiring additional test hardware.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Bibhas Ghoshal, Chittaranjan Mandal, Indranil Sengupta,