A 1.4×FO4 self-clocked asynchronous serial link in 0.18 µm for intrachip communication

In this paper, we describe a repeater-free asynchronous serial link architecture targeting 1×FO4 bit time for on-chip communication. Non-Return To Zero (NRZ) Data/Strobe code is used in the channel to achieve the target speed. Timing pulse trains are generated locally and are employed to drive high speed 'transition latches' in the serializer and deserializer. A RLC line model is derived by the HFSS electromagnetic solver. Inverter-based transmitters and receivers are found to perform faster than other circuits. A prototype device having 30 links and fabricated in Tower Semiconductor 0.18μm CMOS process is described. Measurement results show 3.73 Gb/s data rate over 6.1 mm wire interconnect, corresponding to 1.44×FO4 bit time.