Concurrent built-in self-testing under the constraint of shared test resources and its test time reduction

Integrated circuits testing of IP cores embedded in contemporary SoCs is costly. One common strategy to lower the cost of test is to reduce test time through concurrent testing. At present, it is well known that this approach necessitates the cores under evaluations to be assigned different I/O resources. This work demonstrates the feasibility of concurrent execution of two built-in self-tests under a multi-TAP controller design architecture but sharing the same pin group. We also show that the potential test time saved is not more than 45%. The extent of test time reduction is influenced by the length of BIST as well as the existence of test overheads.