Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
4970710 | Integration, the VLSI Journal | 2017 | 14 Pages |
Abstract
This paper proposes a new thermal-aware test data compression technique using dictionary-based coding. Large test data volume and rise in chip temperature during a test, are the two major challenges for the test engineers. Efficient filling of the don't care bits of the test patterns minimises the transition count in the scan chains, which in turn reduces the temperature of the chip to a large extent. On the other hand, high test data compression can be achieved by filling the don't-cares in a manner to get more similar sub-vectors within the test vectors. Although, both the problems rely on don't-care bit filling, most of the existing works have considered them separately. Moreover, it has been observed that, in general, thermal-aware don't-care filling leads to poor test compression, while a compression-aware don't-care filling produces high temperature. However, a high test compression with low-temperature is the most desirable expectation. In our work, we have combined the temperature reduction and the test data compression into a single problem and solved it. We have presented an integrated approach that can perform a trade-off between temperature and test compression. Experimental results on ISCAS'89, ITC'99 and IWLS'05 benchmarks show the flexibility of the proposed method to achieve a balance between temperature and test compression. The work has further been extended to reduce temperature without sacrificing compression.
Keywords
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Rajit Karmakar, Santanu Chattopadhyay,