Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
4970721 | Integration, the VLSI Journal | 2017 | 15 Pages |
Abstract
A modify wrapper/test access mechanism(TAM) structure is described to explore the maximal potential capacity of TAM, named “IP cores resource multiplexing(IPRM)”, reducing test application time for DVFS-based multicore System-on-Chips(MSoCs). The IPRM core wrappers, different from standard wrappers, enable to isolated core wrapper resource again to store test data for embedded cores under test. An integer linear programming (ILP) formulation with IPRM wrapper is proposed to improve multi-site test. Experimental results of the ITC'02 SoC Benchmark show that IPRM core wrapper reduces the burdens on ATE effectively, and can reduce the test application time by 10-50%.
Keywords
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Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Libao Deng, Baoquan Zhang, Sha Wang, Chengyu Jin,