Analysis and modeling of the semi-floating transistor based 1T pixel in CMOS image sensors

A semi-floating gate transistor (SFGT) based 1 T pixel can achieve the same functions as the traditional 3 T active pixel sensor (APS). The SFGT APS improves the fill factor and the pixel density of CMOS image sensors to meet the requirement for high sensitivity application. This paper proposes an equivalent circuit model for the SFGT APS. The model shows that the intrinsic capacitances and the applied voltages affect the SFG voltage range, the maximum non-saturated light power, the conversion gain and the full well capacity (FWC). The simulation results are obtained by technology computer aided design (TCAD), which shows a good agreement with theoretical calculation. A higher drain voltage improves the output swing, the maximum non-saturated light power, the conversion gain and the FWC. A lower capacitance CPIP increases the output level and the conversion gain at the expense of the light range and the FWC. The model also proposes optimization for better pixel design.