A high accuracy CMOS subthreshold voltage reference with offset cancellation and thermal compensation

This paper presents a high accuracy CMOS subthreshold voltage reference without BJTs for the low-supply-voltage and low-power application. The low supply voltage and low power dissipation are achieved, by making MOSFETs work in the subthreshold region. Besides, the offset scaling down (OSD) technique is proposed for the first time to cancel out the reference voltage variation caused by the offset of the clamping OTA. In addition, the pseudo-series-diodes are used with the negative temperature coefficient (TC) impendence for the second-order thermal compensation. Finally, the proposed voltage reference circuit is implemented in a standard 0.13 µm CMOS process, while the active silicon area is about 0.15×0.24 mm2. At the minimum supply voltage 0.6 V, the measured results shows a TC of 12.8 ppm/°C in the range of −25-85 °C, and total power consumption of 373 nW. The line regulation is 0.15 mV/V in the supply voltage range of 0.6-1.8 V, and the variation of the reference voltage (σ/μ) is 1.28% without trimming and 0.42% after trimming, respectively. The power supply rejection ratio (PSRR) without any filtering capacitor at 1000 Hz is −51 dB for 0.6 V supply and −73.8 dB for 1.8 V supply, respectively.