Article ID Journal Published Year Pages File Type
4971204 Microelectronics Journal 2017 8 Pages PDF
Abstract
As the supply voltage decreasing to near 1 V, the output swing of the CS-DAC (current-steering digital-to-analogue converter) is limited by the minimum biasing voltage of the current source array, which is approximately 0.4 V. This voltage takes one-third of the 1.2 V power supply, which makes the single-ended CS-DAC not practical. To eliminate the output swing limitation, a voltage-controlled current source (VCCS) is proposed to realize high-swing single-ended voltage output for CS-DAC. The VCCS has the same input voltage as the biasing voltage. It generates a matching output current to make the minimum output voltage of the single-ended CS-DAC be able to reach the ground. The VCCS adopts a cascode structure in the output path, thus its performance is independent of DAC output changes. Careful matching is made inside VCCS, as well as between VCCS and DAC. Consequently, this design is robust to the process, supply voltage, and temperature (PVT) variations. The proposed CS-DAC, implemented by 180-nm CMOS technology, has a 1 V output swing under 1.25-1.5 V power supply at 25 °C temperature. For all PVT variation corners, the measured minimum DAC output voltage, designed as 0.11 V, varies between 0.05 V and 0.113 V. The measured DNL and INL are normally less than 0.2 LSB and 0.5 LSB, respectively. The measured slewing time for rising and falling step input are 80 ns and 90 ns, respectively. The measured total power consumption is 1.5 mW.
Related Topics
Physical Sciences and Engineering Computer Science Hardware and Architecture
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