A 0.3 V 8-bit 8.9Â fJ/con.-step SAR ADC with sub-DAC merged switching for bio-sensors

An 8-bit 10 kS/s 0.3 V ultra-low power successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. On account of the presented sub-DAC merged switching scheme reducing the switch energy by 98.4% compared with conventional switching architecture, the energy consumption of the SAR ADC is decreased drastically. Furthermore, a presented double-bootstrapped switch with leakage reduction technologies improves sampling linearity under 0.3 V. In addition, to relieve non-linearity, boost technique is introduced in digital-to-analog converter (DAC) driving switch. The proposed ADC has been fabricated in 180 nm 1.8 V CMOS process. The measurement results show that effective number of bits (ENOB) of the ADC is 7.21 bit at the Nyquist input frequency and 0.3 V supply voltage, achieving a figure-of-merit (FOM) of 8.9 fJ/conversion-step. The chip area is 0.084 mm2.