Analysis and design of cross-coupled charge pump for low power on chip applications

This paper provides a comprehensive analysis of the operation of the CMOS charge pump, leading to a theoretical framework to aid low power designers in the optimization of its design in power constrained applications. An expression for the efficiency is derived as well as the optimum devices dimensions to maximize the latter for a given set of conditions (supply voltage, load current process parameters, etc.). The theory is verified through circuit simulations in Cadence environment using a CMOS 0.18 µm 6-metal layers technology.