Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
4971586 | Microelectronics Reliability | 2017 | 5 Pages |
Abstract
Understanding the impact of process variability on TDDB is crucial for assuring robust reliability for current and future technology nodes. This work introduces a lifetime prediction model that considers local field enhancement to assess the combined impact of die-to-die spacing variability and line edge roughness. The model is applied to 16Â nm half-pitch BEOL interconnects assuming either the power law or the root-E as field acceleration model and the impact on lifetime reduction is discussed. In comparison with the ideal case of a straight line with a nominal spacing of 16Â nm, a 1-sigma spacing variation of 0.6Â nm and 1-sigma LER of 1Â nm leads to ~Â 3 orders of magnitude lifetime reduction when assuming power-law whereas this value is ~Â 1 order of magnitude when assuming root-E.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
D. Kocaay, Ph.J. Roussel, K. Croes, I. Ciofi, Y. Saad, I. De Wolf,