Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
4971800 | Microelectronics Reliability | 2016 | 7 Pages |
Abstract
Reliability evaluation methodologies have become important in circuit design. In this paper, we focus on the probabilistic transfer matrix (PTM), which has proven to be a gate-level approach for accurately assess the reliability of a combinational circuit with penalty in simulation runtime and memory usage. In order to improve its efficiency, several methodologies based on traditional PTM are proposed. A general tool is developed to calculate the reliability of a circuit with efficient computation methods based on an optimized PTM (denoted as ECPTM), which achieves runtime and memory usage improvement. Experiments demonstrate how the proposed simulation framework, combined with traditional PTM method, can provide significant reduction in computation runtime and memory usage with different benchmark circuits.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Hao Cai, Kaikai Liu, Lirida Alves de Barros Naviner, You Wang, Mariem Slimani, Jean-François Naviner,