High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator

•This paper presents a CMOS low quiescent current output-capacitorless LDO regulator.•The proposed LDO is based on a high slew rate current mode transconductance amplifier (CTA).•The order of transfer characteristic of the circuit is increased by using a LCMFB in the CTA.•The slew rate at the gate of pass transistor is enhanced improving load transient characteristic.•The proposed LDO topology has been designed and verified in a 0.18 µm CMOS process.

This paper presents a CMOS low quiescent current output-capacitorless low-dropout regulator (LDO) based on a high slew rate current mode transconductance amplifier (CTA) as error amplifier. Using local common-mode feedback (LCMFB) in the proposed CTA, the order of transfer characteristic of the circuit is increased. Therefore, the slew rate at the gate of pass transistor is enhanced. This improves the LDO load transient characteristic even at low quiescent current. The proposed LDO topology has been designed and post simulated in HSPICE in a 0.18 µm CMOS process to supply the load current between 0 and 100 mA. The dropout voltage of the LDO is set to 200 mV for 1.2–2 V input voltage. Post-layout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10 and 100 pF. The total quiescent current of the LDO including the current consumed by the reference buffer circuit is only 3.7 µA. A final benchmark comparison considering all relevant performance metrics is presented.