Article ID Journal Published Year Pages File Type
538414 Integration, the VLSI Journal 2014 11 Pages PDF
Abstract

•An extensive survey of previous work on mesochronous and related synchronizers.•A proof that at least four buffer stages are generally required in a mesochronous synchronizer.•An analysis of the impact of wire delays and clock drifts on mesochronous synchronization.•Novel architecture of full throughput standard-cell extendable mesochronous StarSync synchronizer.

StarSync, a mesochronous synchronizer, enables low latency and full throughput crossing of clock domain boundaries having same frequency but different phases. Full back pressure is supported, where the receiver can start and stop accepting words without any data loss. Variable depth buffering is provided, supporting a wide range of short and long range communications and accommodating multi-cycle wire delays. Burst data can also be accommodated thanks to buffering. Dynamic phase shifting due to varying voltage and temperature are mitigated by increasing the separation between write and read pointers. The synchronizer is exposed to metastability risk only during reset. It is suitable for implementation using standard cell design and requires neither delay lines nor other full custom circuits. It is shown that a minimum of four buffer stages are required, to mitigate skew in reset synchronization, in contrast with previous proposals for three stages.

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