Domino logic designs for high-performance and leakage-tolerant applications

Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose several domino logic circuit techniques to improve the robustness and performance along with leakage power. Lower total power consumption is achieved by utilizing proposed techniques. According to the simulations in TSMC 65 nm CMOS process, the proposed circuits increase noise immunity for wide OR gates by at least 3.5X and shows performance improvement of up to 20% compared to conventional domino logic circuits. For FinFET simulation TCAD tools have been used.

► New domino logic circuits using CMOS 65 nm technology are proposed and simulated. ► A domino logic circuit using FinFET is presented and simulated using TCAD tools. ► The proposed circuits increase noise immunity by at least 3.5X. ► Proposed designs improve performance compared to conventional domino logic design.