Ultra-low-power signaling challenges for subthreshold global interconnects

Demand of power efficient circuits has grown significantly due to fast growth of battery operated portable applications. Though, subthreshold operation of device shows huge potential towards satisfying the ULP requirement, it holds many challenging design issues. As integration density of interconnect increases at every technology node, increased delay and crosstalk become more challenging design issues particularly for subthreshold interconnects. Nanometer subthreshold interconnect faces subthreshold driver design challenges and problems due to increased interconnect capacitance. This paper explored the suitability of different conventional interconnects strategies and challenges to reduce the total path delay. It also proposed device and interconnect optimization techniques to achieve higher performance and to reduce crosstalk in future subthreshold global interconnects. The effect of variability on subthreshold interconnects have also been investigated.

► It is important to reduce the power in case of portable applications to nW range. ► Superthreshold interconnect techniques are not suitable for subthreshold circuits. ► Interconnect optimization under subthreshold condition is crucial to achieve ULP. ► New interconnect design techniques are explored to enhance ULP circuit performance. ► Crosstalk effect, process and temperature variability effects have been explored.