High-speed full adder based on minority function and bridge style for nanoscale

In this paper a new high-speed and high-performance Full Adder cell, which is implemented based on CMOS bridge style and minority function, is proposed. Several simulations conducted at nanoscale using different power supplies, load capacitors, frequencies and temperatures demonstrate the superiority of the proposed design in terms of delay and power-delay product (PDP) compared to the other cells. In addition the proposed structure improves the robustness and reduces sensitivity to the process variations of the other Bridge-Cap Full Adder cell already presented in the literature.