Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
538668 | Integration, the VLSI Journal | 2008 | 11 Pages |
Abstract
Congestion estimation is an important issue for design automation of the VLSI layout. Fast congestion estimation provides an efficient means to adjust the placement and wire planning. A probabilistic model of interconnections enables designers to quickly predict routing congestion. We propose a powerful and fast estimation approach that allows wires to have bounded-length detours to bypass congestions. The method is more realistic and precise than the previous work. The experimental results demonstrate the effectiveness of the method on routing benchmarks.
Related Topics
Physical Sciences and Engineering
Computer Science
Hardware and Architecture
Authors
Lerong Cheng, Xiaoyu Song, Guowu Yang, William N.N. Hung, Zhiwei Tang, Shaodi Gao,