Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing

•Multi-layer interconnect power optimization under timing constraints is described.•Related global optimization problem is formulated.•An algorithm for solving optimization problem is described and implemented.•A mathematical relation to similar optimization problems is developed.•5–12% dynamic interconnect power reduction on industrial cases is demonstrated.

Reduction of interconnect delay and interconnect power has become a primary design challenge in recent CMOS technology generations. Spacing between wires can be modified so that line-to-line capacitances will be optimized for minimal power under timing constraints. In this paper, we present a novel algorithm for simultaneous multilayer interconnect spacing that minimizes the total dynamic power dissipation caused by an interconnect, while maximum delay constraints are satisfied. A multi-dimensional visibility graph is used to represent the problem, and a layout partitioning technique is applied to solve the problem efficiently. The algorithm was evaluated on an industrial microprocessor designed using the 32 nm technology, and it achieved a 5–12% reduction in interconnect switching power.