ADPLL design parameters determinations through noise modeling

This paper presents a methodology to determine all-digital phase-locked loop (ADPLL) circuit variables based on required design specifications, including output phase noise, fractional spur and locking time. An analytical model is developed to characterize the effects of different noise sources on ADPLL output phase noise and fractional spur. Applying the proposed noise model, circuit variables in ADPLL can be properly selected to meet phase noise, fractional spur and locking time requirements. For model validation, we collect ADPLL circuit designs published in recent literatures and perform model analysis. The analysis results and hardware measurements obtain good agreements.