Article ID Journal Published Year Pages File Type
539688 Integration, the VLSI Journal 2014 8 Pages PDF
Abstract

•The paper proposes a block bulk isolation strategy for triple-well processes.•The substrate noise sensitivity of the designed BGR output is improved more than 100 dB up to 100 MHz.•The designed BGR achieves the best untrimmed temperature coefficient with minimum area.•Its noise performance is equivalent to the best reported [14] while occupying 1/2.5 the area.

This paper presents the design of a low-drift, curvature-corrected bandgap voltage reference (BGR) realized in a 0.35μm 3.3 V triple-well CMOS technology having vertical NPN BJT transistors. The proposed circuit takes advantage of a block bulk isolation strategy improving the substrate noise sensitivity at the BGR output more than 100 dB up to 100 MHz. The simulated circuit achieves a mean temperature coefficient of 6.2 ppm/°C over the temperature range of −40 to 125 °C with 4.1 ppm/°C standard deviation without any trimming. The circuit operates down to 2 V and consumes 31.5μA from a single 3.3 V supply. Its line regulation is less than 0.07% per Volt while its supply voltage changes from 2 V to 3.6 V. The power supply rejection (PSR) of the circuit is −76.5 dB at 100 Hz. The peak-to-peak output noise is 4.66μV integrated within the frequency range of 0.1–10 Hz. The proposed circuit occupies an area of (515μm×320μm) 0.165 mm2.

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Physical Sciences and Engineering Computer Science Hardware and Architecture
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