A PLL-based synthesizer for tunable digital clock generation in a continuous-time ΣΔΣΔ A/D converter

In this paper, the design and implementation of a tunable clock synthesizer for driving two continuous-time ΣΔΣΔ ADCs has been carried out. A PLL-based solution, whose phase noise requirements are obtained from system level simulations, was implemented in a 0.35μm CMOS technology. The frequency of the clock ranges from 12 to 256 MHz with a minimum tuning step of 10kHz. The PLL phase noise is kept below -80dBc/Hz at 1 MHz offset for the entire output range, while drawing 2.2–5.6 mA from a 3.3 V supply voltage.