Low-power design techniques for scaled technologies

Scaling of transistor feature sizes has provided a remarkable advancement in silicon industry for last three decades. However, while the performance increases due to scaling, the power density increases substantially every generation due to higher integration density. Furthermore, the demand for power-sensitive design has grown significantly in recent years due to tremendous growth in portable applications. Consequently, the need for power-efficient design techniques has grown considerably. Several efficient design techniques have been proposed to reduce both dynamic as well as static power in state-of-the-art VLSI circuit applications. In this paper, we discuss different circuit techniques that are used to maintain the power consumption (both static and dynamic) within a limit while achieving the highest possible performance.