A high performance 5 stage pipeline architecture for the H.264/AVC deblocking filter

•High-performance pipeline architecture for the H.264/AVC deblocking filter.•High-throughput ASIC and FPGA implementations.•High-speed and low-area circuit implementation of the deblocking filter.•Support of the H.264/AVC high profiles.•Overlapped computations and efficient distribution of them at the pipeline stages.

Exploiting specific properties of the algorithm, a high-throughput pipelined architecture is introduced to implement the H.264/AVC deblocking filter. The architecture was synthesized in 0.18 μm technology and the clock frequency and area are 400 MHz and 16.8 Kgates, respectively. Also, it is able to filter 217 and 55 Frames per second (Fps) for Full- and Ultra-HD videos, respectively. The introduced architecture outperforms similar ones in terms of frequency (1.8× up to 4×), throughput, (1.5× up to 3.8×), and Fps. Moreover, extensions to support different sample bit-depths and chroma formats are included. Also, experimental results for different FPGA families are offered.