Assignment of inter-die signals in a simplified wiring model for die-stacking SiP designs

•The crossing constraint in a simplified wiring model is defined for the assignment of inter-die signalsin a 3D SiP design.•An ILP-based approach is proposed to assign all the inter-die signals to minimize the total wirelength in a 3D SiP design.•The experimental results show that our proposed approach obtain better results than previous published works.

Compared with traditional flow in IC designs, the assignment of the inter-die signals between different dies is an important stage in a die-stacking SiP design. In this paper, given a tolerant spacing rule between two inter-die signals, the crossing constraint between two inter-die signals can be firstly defined for the bonding wires in a die-stacking SiP design with a simplified wiring model [7]. Furthermore, based on the connection constraint on any inter-die signal, the capacity constraint on any assigned pad on dies and the crossing constraint between two inter-die signals, an integer linear programming-based (ILP-based) approach is proposed to assign all the inter-die signals to minimize the total wirelength in a die-stacking SiP design. Compared with Lin’s two-stage approach [4] for some tested examples without a tolerant spacing distance between two inter-die signals in an Euclidean wiring model, the experimental results show that our proposed ILP-based approach increases 4.5% of CPU time and reduces 6.2% of total wirelength to assign all the inter-die signals on the average. Besides that, compared with Yan’s iterative approach [6] for some tested examples without a tolerant spacing distance between two inter-die signals in an Euclidean wiring model, the experimental results show that our proposed ILP-based approach uses reasonable CPU time to reduce 5.3% of total wirelength to assign all the inter-die signals on the average. Compared with Lin’s modified two-stage approach and Yan’s modified iterative approach for some dense tested examples with a tolerant spacing distance between two inter-die signals in a simplified wiring model [7], the experimental results show that Lin’s modified two-stage approach only achieves 95.9% of the assignment ratio on the average, Yan’s modified iterative approach only achieves 96.6% of the assignment ratio on the average and our proposed ILP-based approach uses reasonable CPU time to achieve 100% of the assignment ratio.