High-level parameterizable area estimation modeling for ASIC designs

•A simple yet accurate high-level area estimation method for ASIC designs is proposed.•The method allows parameterizable area models to be created.•The method can be applied very early in the design process and requires minimal information about the implementation technology.•Application to several real world design examples is presented.•The gate count estimate accuracies are mostly within 5% for real world cases.

Architectural design space exploration and early area budgeting for ASIC and IP block development require accurate high level gate count estimation methods without requiring the hardware being fully specified. The proposed method uses hierarchical and parameterizable models requiring minimal amount of information about the implementation technology to meet this goal. The modeling process flow is to: (1) create a block diagram of the design, (2) create a model for each block, and (3) sum up estimates of all sub-blocks by supplying the correct parameters to each sub-model. We discuss the model creation for a few parameterized library blocks as well as three communication blocks and a processor core from real IC projects ranging from 22 to 250 kgates. The average relative estimation error of the proposed method for the library blocks is 3.2% and for the real world examples 4.0%. The best application of this method is early in the design phase when different implementation architectures are compared.